(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of cleaning PBGA packages that results in reduced-cost cleaning procedures while maximizing the frequency of cleaning cycles.
(2) Description of the Prior Art
The continuing decrease in semiconductor device dimensions coupled with the continuing increase in device densities have, over the years, led to the development of a number of packaging techniques for the packaging of very dense and complex semiconductor devices. Increased device complexity further required improved methods of accessing the semiconductor devices by means of the device input/output (I/O) connections. To accommodate an increased number of I/O connections, semiconductor packages have evolved from lead frame packages such as the Dual In Line (DIL) and Quad Flat Package (QFP) to laminated packages such as the Ball Grid Array (BGA) package.
Concurrent with the use of various packaging techniques, methods and processes have been developed that are aimed at providing increased protection to the packaged semiconductor devices. Where semiconductor devices are mounted on a supporting substrate, such as a Printed Circuit Board (PCB), these devices are typically encapsulated prior to their mounting on the PCB so as to minimize physical damage to the devices and the fragile interconnecting wires or circuitry that are used to interconnect the semiconductor devices. Not only does the encapsulation prevent physical damage to the packaged device, the encapsulation also isolates the packaged device from the environment and in this manner prevents corrosive effects on device components and wiring that can result from contact with moisture or from surface oxidation.
The packaging arrangements that are typically used for the packaging of semiconductor devices employ a number of different approaches, whereby these approaches can be distinguished between methods of providing a (rigid or flexible) support structure on which the semiconductor device is mounted with interconnect lines provided on the surface of the support structure, methods of providing a chip-on-surface mounting technique whereby the supporting structure can comprise laminated layers of interconnect lines that are used in combination with interconnect lines on the surface of the supporting structure and methods of providing laminated packages that use cavities for the mounting of the semiconductor devices. Where possible, the methods of packaging are designed such that automated packaging processes can be used for obvious reasons of costs incurred as part of the packaging process. In this respect, the supporting structure that uses a cavity for the mounting of the semiconductor device does not lend itself to automatic packaging processes since, for the various packaging approaches that have been highlighted, the semiconductor device must, after it has been packaged, as yet be encapsulated, which is a processing step that cannot readily be monitored using cavity based supporting structures.
For the process of encapsulating the semiconductor device, transfer molds are typically used whereby the transfer mold is, during the process of encapsulation, positioned over the to be encapsulated device and removed from that location after the encapsulation has been completed. Using this process, the encapsulant covers at least the semiconductor device and any surrounding (wire bonded) interconnect wire but may, in addition, cover larger surface portions of the supporting structure.
For a typical mounting of a chip on the surface of a laminated substrate, whereby the substrate can be either ceramic (making the substrate rigid) or can contain an organic or plastic material (making the substrate flexible), electrical interconnect lines are formed within the laminated layers of the substrate using conventional methods of metal deposition and patterning that apply standard photolithographic methods and procedures. The various layer of the laminated substrate are insulated from each other using dielectric materials such as a polyimide that can be used to separate for instance metal power and ground planes in the substrate. Electrical connections between the layers of the laminated substrate are formed by conductive vias, the opening of the via is, after this opening has been formed, filled with a conductive material in order to establish the electrically conductive path between the various layers. After the required interconnect patterns have in this manner been established in the laminated substrate, the semiconductor chip is positioned on the surface of the substrate and attached to the substrate by a suitable die attach material such as epoxy. This layer of epoxy serves not only to hold the semiconductor die in place but also serves as a heat transfer medium between the die and the substrate. The top surface of the semiconductor die is connected (wire bonded) to the conductive traces on the surface of the substrate after which the die including the bonded wires can be encapsulate. Electrical interconnects must then be established between the substrate (to which the die is at this time connected) and the surrounding electrical circuits to which the substrate is connected. Electrical traces have also been provided in the lower surface of the substrate, a solder mask is deposited over the bottom surface of the substrate, contact balls are positioned in alignment with the contact points in the lower surface of the substrate and re-flowed thereby connecting the contact balls with the electrical traces in the bottom surface of the substrate and completing the interconnects between the (surface mounted) semiconductor die and the contact balls of the supporting substrate. The method described above is a method of connecting a semiconductor device using wire bond techniques. In addition and as a substitute to the wire-bonding techniques, known connection techniques in the art such as flip-chip techniques can be applied to interconnect the semiconductor die.
The above indicated method of packaging a semiconductor die employs one (lower) mold, the process of applying the mold compound typically uses an upper mold that matches with and overlays the lower mold. Suitable recesses are formed in this case in both the lower and the upper mold in order to enable and facilitate the process of applying the mold around the semiconductor device. During the process of applying the mold compound over the semiconductor die, the die that at this time has been mounted on the surface of a substrate, is inserted with its substrate into a cavity that has been provided for this purpose in a lower mold. An upper mold is aligned with the lower mold, a recess has for purposes of alignment (between the two molds) been provided in the upper mold while a matching opening is provided in the lower mold. An alignment pin is inserted through the opening in the lower mold after which the alignment opening in the upper mold is aligned with the alignment pin that protrudes through the lower mold.
The upper mold contains a cavity that has the internal contours of the mold that needs to be applied over the semiconductor die. After the upper mold has been aligned with the lower mold, the mold cavity in the upper mold overlays the semiconductor die that has been inserted in the lower mold and that is mounted on a laminated substrate. The mold material is then inserted, typically using the same opening that is used to insert the inter-mold alignment pin, from where the mold is forced via a channel (that is provided between the upper and the lower mold) into the mold cavity of the upper mold.
Manufacturing automation and the control of the cost that is incurred during the molding (encapsulation) process requires that the process of molding of the devices can proceed applying the mold to a number of devices in a relatively rapid sequence whereby a number of devices are processed simultaneously. This leads to the processing of multiple substrates simultaneously, the multiple substrates are provided and handled in strip form. The multiple substrates are interconnected and form a substrate strip, after the molding process has been completed the substrates are separated or singulated from each other. This process is further described below.
It must further be realized that, concurrent with substrate strips, multiple molds are typically contained within one mold bar during the process of inserting the mold compound. These mold bars are individually removable, the mold bars can be differentiated between upper and lower mold bars. The upper and lower mold bars are further mounted in and supported by an upper and a lower mold frame and can be readily removed from the mold frames such that flexibility and easy convertibility from one type of mold to the other is provided. The source of the mold that is inserted over the semiconductor die is referred to as the mold pot, it is common practice to provide a multiplicity of mold pots on a separate bar (the runner bar) that is mounted between two adjacent mold bars and that serves to supply the mold compound to the individual molds for simultaneous molding.
FIG. 1 shows a top view of a substrate strip 10 that contains four individual substrates 12. Openings 14 have been provided in the substrate strip 10, these openings are used for attachment of the substrate strip 10 to other processing equipment during additional processing steps, these processing steps are not further described at this time. Stress relieve between the individual substrates 12 and the substrate strip 10 is provided by the substrate separation slots 16. These separation slots assure that the substrates 12, although the substrate 12 are interconnected to and are part of the substrate strip 10, act as individual units and do not incur warp or any other stress related deformity during the handling of the substrate strip 10 or at the time that the substrates 12 are singulated. Each of the corners of the substrates 12 is further provided with an opening 18, which improves the singulation results by providing a well controlled circumference of the singulated substrate. The semiconductor die or chip is placed in the middle of each of the substrates 12, these die placement areas are highlighted as areas 20.
The substrates 12 that are shown in FIG. 1 are the laminated substrates that have previously been described and contain layers of interconnect lines and points of electrical interconnect on both surfaces of the substrate. These interconnect points are, for reasons of clarity, not shown in FIG. 1. The laminated substrate 12 shown in FIG. 1 are the substrates that are further used for the creation of BGA packages and package interconnects. The substrates 12 are, in other words, desired end products of a processing sequence, these substrates 12 are only indirectly related to the invention.
U.S. Pat. No. 5,886,398 (Low et al.) shows a process that involves a transfer molding and substrate and singulation. The molded packages have an internal mold gate. However, this reference differs from the invention.
U.S. Pat. No. 5,780,933 (Ohmori) shows a package using a transfer molding. However, this reference differs from the invention.
U.S. Pat. No. 5,795,799 (Hosoya) shows a molding process with transfer molding.
U.S. Pat. No. 5,939,778 (Boutin et al.) shows a related molding process.
A principle objective of the invention is to provide an improved method of cleaning of mold material that is typically used to encapsulate BGA devices.
In accordance with the objectives of the invention a new method is provided to clean melamine deposits from tools and components that are used to form molds around and to therewith encapsulate BGA devices. The cleaning process applies a dummy BGA substrate as part of and during the cleaning procedure. This dummy BGA substrate replaces the conventionally used copper strips that shield areas of the molding tools during the cleaning cycle. The dummy copper strips require, during and as part of the melamine cleaning process, frequent cleaning, which adds considerable to the time and expense of the melamine cleaning process.